In systems that transmit and receive (e.g., transceivers) data at high rates (or high bandwidths), both the speed at which data is transmitted or received and the reliability and stability of such data may be important.
In data transmission systems that use system clocks for control and high-speed operations, data or control signals may be synchronized to a system clock or be transmitted within a desired time frame based on the system clock. However, the time at which signals are transmitted may vary due to noise, circuit mismatches or inconsistent data patterns.
As the timing variations deteriorate, an effective data window may become narrower. This may make it more difficult to accurately receive data. That is, a receiver's ability to ensure that data is correctly received may be reduced. Moreover, such a problem may be more pronounced in systems where data is transmitted at a high-rate of speed.
For example, in a transceiving system operating in a current mode that includes a rambus DRAM (RDRAM), a data bit which is transmitted first (a signal bit transmitted first after a long waiting state) may exhibit a larger timing variation because an efficient set up time may not be guaranteed with respect to the first bit under the condition of reducing the system latency. Generally, if data cannot be read, a logic state “0” is assigned. The result being, for example, that a data pattern becomes unreliable when the first data bit indicating “1” is read instead as a “0”.
Other problems may also occur related to individual circuits. FIG. 1 illustrates an output driver 1 operating in a current mode of an RDRAM. A signal ENVG 2 applied to a gate of output transistor M1 has settled at a specific voltage before the data bit DATA 3 shown in FIG. 2A is applied to a gate of output transistor M2. Thereafter, data is output to a data channel (DC) 4 in response to a logic state (e.g., “0” or “1”) of the data bit DATA 3. Sometimes, however, data may be output before the signal ENVG has had a chance to stably settle at a specific voltage. This may lead to data transmission timing variations and errors.
Further, node N1 between the output transistors M1 and M2 may be precharged to reduce channel noise. In conventional systems, a precharge voltage may be coupled with the voltage associated with a first data bit output from transistor M2. The first data bit has the highest voltage ΔVi (the other data bit is ΔVn), as shown in FIG. 2B, such that the timing is deteriorated.
FIG. 3 illustrates differences in a timing variation, ΔTQ, between the first data bit and subsequent data bits under specific process, voltage and temperature conditions. The timing variation, ΔTQ, shows an irregular distribution over the range of 0-36 pico-seconds (ps).